The present invention relates to microprocessors (including microcontrollers and microcomputers), and particularly to microprocessors having a low-power standby state.
The DS5000 Soft MicroController.TM., marketed by Dallas Semiconductor, Inc., is a microcontroller which has a small battery packaged with it, to provide nonvolatility. Microprocessors and microcontrollers of this kind are extremely useful, since the internal memory of the microprocessor is always preserved. Therefore, the microprocessor can be programmed to "learn" while in service, or to internally store a parameter set which is adjustable throughout the lifetime of the microprocessor. The present invention provides an improvement in such microprocessors.
Since the internal memory is normally closely integrated with the logic portions of the microprocessor, providing standby power to the memory portions necessarily means that standby power will be provided to other parts of the microprocessor as well. However, this can cause problems.
A common type of manufacturing defect, in manufacturing integrated circuits, is the creation of transistors which are slightly leaky when they are supposed to be in an off state. While such transistors may function perfectly well during normal operation, and the total of leakage current of this kind may not degrade the total power consumption of the chip excessively during normal operation, this additional leakage can be disastrous when the chip is being powered by a battery back-up. Chips for such applications may draw current, in the standby mode, which is of the order of nanoamperes, so that a small amount of additional leakage can drastically increase the standby current draw. Where the chip must be able to retain data for 10 years, even a very small leakage current may exhaust the battery long before 10 years have passed.
For many devices on the chip, testing procedures can be used to detect whether such leakage is occurring. However, not all transistors can be tested in this fashion. The possiblities for testing a particular transistor are dependent not only on its circuit interconnections, but also on the logic state that the circuit happens to be in. That is, if a particular transistor is in the "on" state, it will not be possible to detect whether it would have excess leakage current if it were in the "off" state. A chip can readily be tested to determine if leakage is excessive in a given state; but chips cannot readily be tested for excess leakage in all states.
That is, it has been discovered by the inventors of the present application that an additional reliability constraint, in addition to those normally tested for, exists in such battery-backed applications of very complicated integrated circuits. The entry into standby mode cannot simply save the existing state of the microprocessor, since the number of possible states is immense, and it would not be possible to test each of these states for unacceptable leakage.
Thus, for a nonvolatized microprocessor with a battery-driven power supply in its standby mode, it is necessary to be able to test the state in which the microprocessor will remain during its standby mode. It is not practical to preserve the full set of possible states of the microprocessor when the microprocessor shifts over to its standby mode. Therefore, it is necessary to bring the microprocessor to a known state when entering standby mode.
Normally, when it is desired to put a microprocessor into a known state, this is done by activating a reset. Some microprocessor architectures have reset lines running to every resettable storage element on the chip, so that a reset command will instantly reset every logical element to a known state. However, some architectures do not. For example, in the Intel 8051 architecture, several cycles are necessary after the reset command, to clock all of the logical elements on the chip into the known state. (This architecture is used not only in Intel's 80C51 microprocessor, but also in any other microprocessor which is to be compatible with this widely-used architecture). For example, a simple example of a logic block which would require multiple cycles to reset would be a shift register, with a reset only at the input of the shift register. In this (hypothetical) case, it can be seen that, even after the reset command has provided a known state in the first stage of the shift register, unknown data may still exist in the following stages. Therefore, a series of clock commands must be provided, to propagate the known state all the way through the shift register.
Many microprocessor architectures of interest will have some sequential logic on chip. This sequential logic may not necessarily be provided with sufficient reset lines to reset all of it in one step. However, note that this creates problems in bringing a battery-backed nonvolatile microprocessor to a known state on power-down.
Typically, a power supply smoothing capacitor will be provided on the board or elsewhere, so that the power supply voltage seen by the microprocessor will change with a moderately long time constant (e.g. of the order of milliseconds) when power goes down. Thus, a voltage comparator can detect when the power supply is crashing, in time for the microprocessor to execute a command sequence to enter the predetermined state.
However, the present invention teaches that, in order to do this reliably, the system clock should not be relied on. That is, when the power supply is crashing, the system clock may have already stopped by the time the comparator detects that the power supply is going down. Thus, the system clock cannot be relied on to perform the additional clocking to place the microprocessor in the known state.
In the present invention, an on-chip clock is provided to generate the additional clock cycles needed after reset to enter the known state. Clock intercept logic is also provided, to disconnect the system clock when the power-down sequence is entered, and activate the internal clock.
The internal clock generation circuitry need only clock the internal circuitry sufficiently accurately to converge on the predetermined logic state. Thus, the internal clock generator can be made relatively simple. Thus, the present invention provides a microprocessor which can reliably retain all the data in its internal memory during power-down status for extremely long time periods.
As noted, microprocessor architectures which provide single-step full entry into the reset phase do not require as elaborate operations to enter a predetermined state at power-down. However, a number of considerations favor architectures which do not provide this one-step reset: First, in the microprocessor industry, compatibility is an absolutely crucial issue. Several well-accepted current microprocessor architectures require multi-step reset operations. Second, many useful circuit blocks are inherently multi-phase state machines, and the ability to use such circuitry without adding a plethora of reset lines makes the layout easier and more compact. Third, in designing programmable logic, the metal layout is much simpler if it is not necessary to provide reset lines to every latch on the chip. That is, for a fully one-step reset operation, a reset line must be provided to precondition every single latch on the chip. There are a great many such latches.
Alternatively, if it is necessary to save the state of a microprocessor entering power-down, this can be done separately. For example, a "shadow" memory or register can be used to track the status of various on-chip registers, etc. Similarly, if desired, portions of on-chip memory can even be used as "shadow" scratch pad, to preserve some state information during such power-down operations.